Write down the key features of SCSI PCI BUS

(2) Bus system arbitration

Bus masters are devices on a PCI bus that are allowed to take control of that bus. This is done by a component named a bus arbiter, which usually integrated into the PCI chipset. Specifically, it is typically integrated into the host/PCI or the PCI/expansion bus bridge chip. Each master device is physically connected to the arbiter via a separate pair of lines, with each of them being used as REQ# (request) signal or GNT# (grant) signal, respectively. Ideally, the bus arbiter should be programmable by the system. If it is, the startup configuration software can determine the priority to be assigned to each member by reading from the maximum latency (Max_Lat) configuration register associated with each bus master (see Figure 5.11). The bus designer hardwires this register to indicate, in increments of 250 ns, how quickly the master requires access to the bus in order to achieve adequate performance.

At a given instant in time, one or more PCI bus master devices may require use of the PCI bus to perform a data transfer to another PCI device. Each requesting master asserts its REQ# output to confirm to the bus arbiter its pending request for the use of the bus. In order to grant the PCI bus to a bus master, the arbiter asserts the device’s respective GNT# signal. This grants the bus to a bus master for one transaction, as shown in Figure 5.10. If a master generates a request, it is subsequently granted the bus and does not then initiate a transaction by asserting FRAME# signal within 16 PCI clocks after the bus goes idle, the arbiter may then assume that this bus master is malfunctioning. The action taken by the arbiter would then depend upon the system design. If a bus master has another transaction to perform immediately after the one it just initiated, it should keep its REQ# line asserted when it asserts the FRAME# signal to begin the current transaction. This informs the arbiter of its desire to maintain ownership of the bus after completion of the current transaction. In the event that ownership is not maintained, the master should keep its REQ# line asserted until it is successful in acquiring bus ownership again.

At a given instant in time, only one bus master may use the bus. This means that no more than one GNT# line will be asserted by the arbiter during any PCI clock cycle. On the other hand, a master must only assert its REQ# output to signal a current need for the bus. This means that a master must not use its REQ# line to “park” the bus on itself. If a system designer implements a bus parking scheme, the bus arbiter design should indicate a default bus owner by asserting the device’s GNT# signal when no request from any bus masters are currently pending. In this manner, signal REQ# from the default master is granted immediately once no other bus masters require the use of the PCI bus.

The PCI specification does not define the scheme to be used by the PCI bus arbiter to decide the winner of any competition for bus ownership. The arbiter may utilize any scheme, such as one based on fixed, or rotational priority, or a combination of these two, to avoid deadlocks. However, the central arbiter is required to implement a fairness algorithm to avoid deadlocks. Fairness means that each potential bus master must be granted access to the bus independently of other requests. Fairness is defined as a policy that ensures that high-priority masters will not dominate the bus to the exclusion of lower-priority masters when they are continually requesting the bus. However, this does not mean that all agents are required to have equal access to the bus. By requiring a fairness algorithm there are no special conditions to handle when the signal LOCK# is active (assuming a resource lock) or when cacheable memory is located on the PCI. A system that uses a fairness algorithm is still considered fair if it implements a complete bus lock instead of a resource lock. However, the arbiter must advance to a new agent if the initial transaction attempting to establish a lock is terminated with retry.

1.3.1 ARM BUS TECHNOLOGY

Embedded systems use different bus technologies than those designed for x86 PCs. The most common PC bus technology, the Peripheral Component Interconnect (PCI) bus, connects such devices as video cards and hard disk controllers to the x86 processor bus. This type of technology is external or off-chip (i.e., the bus is designed to connect mechanically and electrically to devices external to the chip) and is built into the motherboard of a PC.

In contrast, embedded devices use an on-chip bus that is internal to the chip and that allows different peripheral devices to be interconnected with an ARM core.

There are two different classes of devices attached to the bus. The ARM processor core is a bus master—a logical device capable of initiating a data transfer with another device across the same bus. Peripherals tend to be bus slaves—logical devices capable only of responding to a transfer request from a bus master device.

A bus has two architecture levels. The first is a physical level that covers the electrical characteristics and bus width (16, 32, or 64 bits). The second level deals with protocol—the logical rules that govern the communication between the processor and a peripheral.

ARM is primarily a design company. It seldom implements the electrical characteristics of the bus, but it routinely specifies the bus protocol.

PCI bus versus ISA bus

Most PCs, until the arrival of the Pentium, were provided with a PC/AT bus (or ISA bus) for connecting peripherals (such as sound cards, frame grabbers and so on). The ISA bus operates with 16 bit data bus and a 16 bit address bus and operates with a divided clock. The ISA bus limits real-world transfer rates to around 1–2 Mbytes/s which is just enough for high-quality, dual-channel audio. The Peripheral Component Interconnect (PCI) bus is incorporated in newer Pentium-based IBM PCs. PCI is a local bus, so named because it is a bus which is much ‘closer’ to the CPU. Local buses run at a much higher rate and PCI offers considerable performance advantages over the traditional ISA bus allowing data to be transferred at between 5 and 70 Mbytes/s; allowing the possibility of real-time, multi-track audio applications. PCI bus is a processor-independent bus specification which allows peripheral boards to access system memory directly (under the aegis of a local bus controller) without directly using the CPU, employing a 32 bit data bus and a 64 bit address bus at full clock speed. Installation and configuration of PCI bus plug-in cards is much simpler than the equivalent installation on the ISA Bus. Commonly referred to as the ‘plug-and-play’ feature of the PCI Bus, this user-transparency is achieved by having the PCs BIOS configure the plug-in card's base address and interrupt level at power-up. Because all cards are automatically configured, conflicts between them are eliminated. A process which can only be done manually with cards on the ISA Bus. The PCI Bus is not limited to PCs; it is the primary peripheral bus in the PowerPC and PowerMacs from Apple. Incorporation of the PCI Bus is planned for other RISC-based processor platforms.

7.4 Summary

This chapter introduced some of the fundamental concepts behind how board buses function, specifically the different types of buses and the protocols associated with transmitting over a bus. Two real-world examples were provided—the I2C bus (a non-expandable bus) and the PCI bus (an expandable bus)—to demonstrate some of the bus fundamentals, such as bus handshaking, arbitration, and timing. This chapter concluded with a discussion on the impact of buses on an embedded system’s performance.

Next, Chapter 8, Device Drivers, introduces the lowest level software found on an embedded board. This chapter is the first of Section III, which discusses the major software components of an embedded design.

8.3.9 Connection to external devices

The ability to connect the computer with devices outside the computer is an important feature. Common devices include printers, memory sticks, projectors for lecture presentation, external mice for laptops, and many others. In engineering, lab and test equipment is often connected to computers, which can then collect and analyze data and even control the testing process. In the early days of computing these connections were made typically in one of two ways. The computer's bus, as described in Section 8.3.7, could be made available to the outside through standard bus extensions, such as the PCI bus. This method provided high-speed access to the device outside the computer. Alternatively, the external equipment could include the standard parallel printer interface and be connected to the computer through its standard printer port. This method was slower but still suitable for many kinds of external equipment. During the period 1970 through 2000, external equipment was provided with serial communication ability and could be connected to the computer through the standard RS232 port. Equipment that required higher speeds used newer parallel interfaces, such as the IEEE-488 bus or the SCSI bus. Since 2010 these have almost all disappeared in favor of the newer very high-speed connections such as USB and HDMI. Newer laptops no longer have parallel ports or RS232 ports.

USB (Universal Serial Bus) was first introduced in 1996. It has undergone several revisions and extensions that allow transmission over longer distances and at much higher speeds than the first version. USB 3.2, released in 2017, can transmit data at speeds up to 20 Gbit/s. USB was meant to connect computers to their peripheral devices, such as disks, keyboards, and mice. Cable length was not an important consideration, and USB cables are limited to 3–5 m depending on the speed of transmission. USB is an asynchronous serial protocol in which data is transmitted using differential drive. A USB A/B cable has four wires—GND, Vcc, D +, and D −. Cables for the later ultra-high speed versions have additional wires for high-speed transmit and receive. USB is a point-to-point protocol. A host device (normally the computer) connects through a USB cable to a device at the other end of the cable. (By contrast, some serial protocols, such as IIC and CAN, allow many devices to attach to the bus and any number of them to act as host at different times.) The other device can be an USB hub, which splits the connection and allows connection to several devices further down the chain. The structure is like a tree, with the host (the computer) as the root of the tree. All USB bus activity is initiated by the host.

HDMI (High Definition Multimedia Interface) was introduced in 2002 to provide a standard connector for the transmission of video and audio data. Like USB it has undergone several revisions. HDMI 2.1, introduced in 2017, has data speeds up to 48 Gbit/s. HDMI cables are limited to 10–13 m due to practical considerations such as signal attenuation, but several companies offer repeater boxes that retransmit an incoming signal to an outgoing port. The HDMI cable itself contains power and GND wires, a pair of wires used for IIC serial transmission, another wire used for special audio transmissions, and four sets of data bundles. Each bundle is a shielded differential drive pair; thus, each bundle has three connections—the shield, positive data, and negative data. Type B cables contain two additional data bundles. Each data bundle is dedicated to a specific type of information related to the video and audio information being transmitted. For example, one is a dedicated clock, another is dedicated to display data, and a third provided for controlling multiple electronic devices with a single remote. HDMI ports on computers are mainly used for transmission of video/audio data from the computer to external devices like projectors, camcorders, and HDTVs. The HDMI standards define protocols for a large number of video/audio related functionalities, such as 3D video, lip-synch, multiple audio channels, and many more. The HDMI port would not typically be used for interface to non-video type lab equipment.

8.3.9 Instrumentation Buses

A computer system can also be extended, as shown in Fig. 8.3, by expanding its bus to include external peripherals such as laboratory equipment designed to feed data to a computer. At the end of Section 8.3.7 on “The Three Buses” some standard system expansion buses such as the PCI bus were discussed. An external bus standard, the RS-232, initially designed to connect modems to computers, already introduced in the previous section, is a bit-serial, asynchronous connection using a 25-wire cable. The RS-232 serial interface port transmits and receives serial data 1 bit at a time. It has been updated as the RS-232C standard and is now used to connect other peripherals such as printers. Most popular PCs provide for RS-232C interfaces.

Manufacturers of laboratory equipment designed to be connected to a computer use a byte-serial interface designated as IEEE-488. It is a general-purpose, parallel instrumentation bus consisting of 16 wires, featuring 8 data lines and 8 control lines. The 8 data lines give this bus a byte-wide data path (“byte-serial” means transmitting and receiving 1 byte at a time). The control lines are used to connect the various instruments together. Each instrument connected to the bus can be in one of four different states: it can be idle, acting as a talker, acting as a listener, or controlling communication between talkers and listeners. IEEE-488 interface electronics are widely available on PCs, allowing laboratory instruments to be connected to this bus. The specification states that the bus can support at most 15 instruments with no more than 4 m of cable between individual instruments and not more than 20 m of overall cable length, with a maximum data rate of 1 megabyte per second (MBps). The intent was to provide interconnection for instruments within a laboratory room of typical dimensions.

SCSI, a parallel bus (although not as true an instrumentation bus as the IEEE-488), was initially developed to interface hard disk and tape backup units to a host computer but has since become a more general-purpose standard. Unlike RS-232C, SCSI can support multiple processors and up to eight peripheral devices, and unlike the IEEE-488 bus, it is not restricted to a single host processor. A 50-wire connector is standard in the SCSI I/O bus, which includes 9 data lines (8 data plus parity) and 9 control lines. Data transfers can take place up to 4 MBps in synchronous mode, decreasing to 1.5 MBps in asynchronous mode. The SCSI protocol is moderately sophisticated. Protocol refers to the set of rules or conventions governing the exchange of information between computer systems: specifically, the set of rules agreed upon as to how data are to be transferred over the bus. Thus, as we have seen, there can be many different ways to transfer data between the CPU and the peripherals, in addition to being classified as synchronous or asynchronous, depending on whether or not the transfer bears a relationship to the system clock. SCSI data transfer can be divided into three primary steps: arbitration, selection, and information. The CPU first checks if the bus is free. If it is, it then takes control of it. During selection, the CPU flags the target peripheral with which it desires to communicate. This is followed by the target responding with the type of information transfer in which it is prepared to engage: data in/out, message in/out, command request, or status acknowledgment. The CPU and peripherals communicate using a set of high-level command bytes, transmitted in packets. Macintosh computers were one of the first to use the SCSI bus.

The separate lines in a multiwire bus are termed traces. One should not readily assume that these bus standards merely involve assignments of particular traces to specific processor functions. Signal traces must be treated as transmission lines which posses distributed capacitance (farads/meter), distributed inductance (henries/meter), and characteristic impedance. This comes about because we cannot treat signals on such lines as propagating with infinite speed and producing the same instantaneous voltages and currents everywhere on the line—as is commonly assumed in electric circuits. The fact is that signals propagate down the line at speeds less than the speed of light, requiring approximately 1.5 ns to travel 1 ft. As the wire length and the signal frequency increases, it becomes more and more essential not to assume zero propagation time but to take the finite propagation time into account. Such transmission lines must be properly terminated (matched), otherwise transmitted signals will be reflected by a receiving device. The reflected signal can severely interfere with the transmission of information in the forward direction. For example, plugging an I/O board of impedance 20Ω into a bus that acts like a transmission line with a characteristic impedance Z0 equal to 100Ω will produce a reflected signal at the board location with voltage equal to (100–20)/(100+20) = 67% of the incident signal voltage. Such a large reflection will introduce significant errors, unless the wire lengths are very short. The matching problem is accentuated for fast computers which carry data in excess of gigabit rates (a gigabit per second digital signal has a gigahertz fundamental frequency with a nanosecond period). Transmission lines and how to properly terminate them is addressed in Section 9.5.5.

6.5.2 PCI bus protocol checkers

The Peripheral Component Interconnect (PCI) bus is being used as an interconnection among high-performance peripherals such as network cards, sound cards, modems, extra ports such as USB or serial and other add-in boards. Although developed by Intel, it is not tied to any particular family of microprocessors [27]. The PCI local bus is a 32-bit or 64-bit bus with multiplexed address and data lines [27] that run at clock speeds of 33 or 66 MHz. For instance, the PCI bus can yield throughput rate of 264 MBps at 64 bits and 33 MHz. Although PCI bus is being replaced by PCI Express, most motherboards are still made with one or more PCI slots, which are sufficient for many uses. In our experiments, we have considered 40 assertion-checkers from [26] that monitor the properties of the PCI bus protocol and perform compliance testing for the devices connected to the bus.

5.4.2.1 Snapshot based introspection

Snapshot based approaches take the snapshot of the memory contents and CPU registers. The snapshots are created at specific intervals with the assistance of hardware components such as System Management Mode (SMM) and Peripheral Component Interconnect (PCI).

What are the features of SCSI bus?

What is the key feature of the PCI bus?

What is PCI and SCSI bus?

What are the advantages of PCI?