Top-level design entity microprocessor_lib is undefined năm 2024
1 LIBRARY ieee ; 2 USE ieee.std_logic_1164.all ; 3 PACKAGE components IS 4 -- 2-to-1 multiplexer 5 COMPONENT mux2to1 LIBRARY ieee ; 0 LIBRARY ieee ; 1 LIBRARY ieee ; 2 LIBRARY ieee ; 3 LIBRARY ieee ; 4 LIBRARY ieee ; 5 LIBRARY ieee ; 6 LIBRARY ieee ; 7 LIBRARY ieee ; 8 LIBRARY ieee ; 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 LIBRARY ieee ; 7 2 8 2 9 USE ieee.std_logic_1164.all ; 0 USE ieee.std_logic_1164.all ; 1 USE ieee.std_logic_1164.all ; 2 USE ieee.std_logic_1164.all ; 3 USE ieee.std_logic_1164.all ; 4 USE ieee.std_logic_1164.all ; 5 USE ieee.std_logic_1164.all ; 6 USE ieee.std_logic_1164.all ; 7 USE ieee.std_logic_1164.all ; 8 USE ieee.std_logic_1164.all ; 9 3 0 3 1 3 2 LIBRARY ieee ; 7 3 4 3 5 3 6 3 7 3 8 USE ieee.std_logic_1164.all ; 3 PACKAGE components IS 0 PACKAGE components IS 1 PACKAGE components IS 2 PACKAGE components IS 3 PACKAGE components IS 4 PACKAGE components IS 5 PACKAGE components IS 6 PACKAGE components IS 7 PACKAGE components IS 8 LIBRARY ieee ; 7 4 0 4 1 4 2 4 3 4 4 4 5 4 6 USE ieee.std_logic_1164.all ; 3 4 8 PACKAGE components IS 1 -- 2-to-1 multiplexer 0 PACKAGE components IS 3 -- 2-to-1 multiplexer 2 PACKAGE components IS 5 -- 2-to-1 multiplexer 4 PACKAGE components IS 7 -- 2-to-1 multiplexer 6 LIBRARY ieee ; 7 -- 2-to-1 multiplexer 8 -- 2-to-1 multiplexer 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 COMPONENT mux2to1 0 COMPONENT mux2to1 1 COMPONENT mux2to1 2 LIBRARY ieee ; 7 COMPONENT mux2to1 4 4 1 COMPONENT mux2to1 6 COMPONENT mux2to1 7 COMPONENT mux2to1 8 COMPONENT mux2to1 9 LIBRARY ieee ; 00 5 3 LIBRARY ieee ; 02 LIBRARY ieee ; 03 LIBRARY ieee ; 04 LIBRARY ieee ; 05 LIBRARY ieee ; 06 LIBRARY ieee ; 7 LIBRARY ieee ; 08 4 1 LIBRARY ieee ; 10 LIBRARY ieee ; 11 LIBRARY ieee ; 12 von Murali B. (nmb) 2013-09-08 13:41 LIBRARY ieee ; 13 LIBRARY ieee ; 14 von Lothar M.(Company: Titel) (lkmiller) (Moderator) 2013-09-09 08:16 LIBRARY ieee ; 15 von Murali B. (nmb) 2013-09-17 16:18 LIBRARY ieee ; 16 Please log in before posting. Registration is free and takes only a minute. How to define topA design entity that is the root of a design hierarchy. To compile or simulate a design, you compile or simulate the top-level design entity. A top-level design entity can contain any number of lower-level design entities (or, subdesigns), and is the parent for the lower-level design entities. How do I change the topIn Quartus II, use "Project --> Set as Top-Level Entity" to change the top-level entity to different VHDL example. Alternatively, highlight the VHDL file name in the "Project Navigator" and right click to select "Set as Top-Level Entity". |